This invention relates to array processors.
An array processor is defined herein as a data processing system comprising a plurality of processing elements which are operable in parallel upon separate data streams under the control of a common stream of control signals. Thus, all the elements perform basically the same sequence of operations (subject to possible modifications by activity bits within the individual elements or by control signals which are specific to particular groups of elements), but on different data. With such a processor, as many operations can be performed simultaneously as there are elements, and hence the data throughput can be very high.
Such a processor may be formed out of a plurality of identical modules, each module including one or more of said processing elements. Each module has a plurality of terminals and the modules may for example be connected together in rows and columns by means of data paths between these terminals, so as to permit transfer of data between adjacent modules. At least one of these terminals may also serve to provide an output signal which is combined (e.g. ANDed or ORed) with other signals from the same row (or column) to provide a row (or column) response signal.
Such a system is described, for example, in our British Patent Specification No. 1,445,714 published Aug. 11, 1976 and in our co-pending British Patent Application No. 10873/76 filed Mar. 18, 1976, now British Patent No. 1,536,933 published Dec. 29, 1978.
It is clear that, if the array contains a large number of modules, a large number of AND/OR gates and data paths is necessary to form the response signals. One object of the present invention is to reduce the number of such gates and data paths.